`ifdef NOSIM

`else
`define DB_LANE_X2
`endif

module bl_data_buf(
		//时钟&复位
		input   wire			resetb,
		input   wire			sclk,
		
		//设置数据
		input	wire			set_clk,
		input	wire			set_d_ok,
		input	wire    [23:0]  set_addr,
		input	wire    [7:0]   set_data,
		
		//调整数据输入
		input	wire			BL_clk,
		input	wire			BL_we,
		input	wire	[12:0]	BL_waddr,
		input	wire	[8:0]	BL_wdata,
		input	wire			BL_we_end,
		input	wire			lock,
				
		//数据读取
		input	wire			v_start,
		input	wire	[6:0]	bl_h_addr,
		input	wire	[6:0]	bl_l_addr,

		//调整数据
		output	reg		[71:0]	bl_data,
		
		//调试信号
		output	wire    [7:0]   tout
		);

//***********************************************/
//				参数定义
//***********************************************/

//***********************************************/
//				信号定义
/************************************************/
reg				hl_info_en;
reg		[9:0]	l_block_addr;
reg		[6:0]	l_block_max;
reg		[6:0]	h_block_max;
//wire	[8:0]	h6_rdata, h5_rdata, h4_rdata, h3_rdata, h2_rdata, h1_rdata, h0_rdata;
wire	[8:0]	h8_rdata, h7_rdata, h6_rdata, h5_rdata, h4_rdata, h3_rdata, h2_rdata, h1_rdata, h0_rdata;

reg				buf_w_sel, buf_r_sel;
reg		[6:0]	l_addr;
reg		[5:0]	h0_addr, h1_addr, h2_addr, h3_addr, h4_addr, h5_addr, h6_addr, h7_addr, h8_addr;

//************************************************/
//					配置参数
//************************************************/	
always@(posedge set_clk or negedge resetb)
	if (resetb == 0) begin
		l_block_addr <= 128;
		l_block_max <= 63;//背光的行分区擿-1
		h_block_max	<= 35;//背光的列分区擿-1
		end
    else if  (set_d_ok == 1)
       case (set_addr[23:0])
            24'h001104:	l_block_addr[7:0] <= set_data;
	        24'h001105:	l_block_addr[9:8] <= set_data[1:0];
            24'h001108:	l_block_max[6:0] <= set_data;
			24'h001138:	h_block_max[6:0] <= set_data;
	   endcase
            
/************************************************/
//      		背光数据缓冲
/************************************************/
swsr_16kx9_sdp bl_h0_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h0_addr, l_addr}),
	.doutb(h0_rdata)
	);

swsr_16kx9_sdp bl_h1_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h1_addr, l_addr}),
	.doutb(h1_rdata)
	);

swsr_16kx9_sdp bl_h2_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h2_addr, l_addr}),
	.doutb(h2_rdata)
	);

swsr_16kx9_sdp bl_h3_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h3_addr, l_addr}),
	.doutb(h3_rdata)
	);

swsr_16kx9_sdp bl_h4_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h4_addr, l_addr}),
	.doutb(h4_rdata)
	);

swsr_16kx9_sdp bl_h5_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h5_addr, l_addr}),
	.doutb(h5_rdata)
	);

swsr_16kx9_sdp bl_h6_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h6_addr, l_addr}),
	.doutb(h6_rdata)
	);

swsr_16kx9_sdp bl_h7_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h7_addr, l_addr}),
	.doutb(h7_rdata)
	);

swsr_16kx9_sdp bl_h8_buf(
	.clka(BL_clk),
	.ena(1'b1),
	.wea(BL_we),
	.addra({buf_w_sel, BL_waddr}),
	.dina(BL_wdata),
	
	.clkb(sclk),
	.enb(1'b1),
	.addrb({buf_r_sel, h8_addr, l_addr}),
	.doutb(h8_rdata)
	);

//*************************************************/
//		数据区切换控儿
//*************************************************/	
//写背光数据帧切换
always @(posedge BL_clk or negedge resetb)
	if (resetb == 0)
		buf_w_sel <= 0;
	else if ((BL_we_end == 1) && (lock == 0))
		buf_w_sel <= ~buf_w_sel;

//读背光帧切换
always @(posedge sclk)
	if (v_start == 1)
		buf_r_sel <= ~buf_w_sel;

/************************************************/
//      读地囿控冿
/************************************************/
//读列地址
always @(posedge sclk)
	if (bl_l_addr > l_block_max)
		l_addr <= l_block_max;
	else
		l_addr <= bl_l_addr;

//读行地址
always @(posedge sclk)
	if (bl_h_addr < 4)
		h0_addr <= 0;
	else
		h0_addr <= bl_h_addr - 4;

always @(posedge sclk)
	if (bl_h_addr < 3)
		h1_addr <= 0;
	else
		h1_addr <= bl_h_addr - 3;

always @(posedge sclk)
	if (bl_h_addr < 2)
		h2_addr <= 0;
	else
		h2_addr <= bl_h_addr - 2;

always @(posedge sclk)
	if (bl_h_addr < 1)
		h3_addr <= 0;
	else
		h3_addr <= bl_h_addr - 1;

always @(posedge sclk)
	h4_addr <= bl_h_addr;

always @(posedge sclk)
	if (bl_h_addr > h_block_max - 1)
		h5_addr <= h_block_max;
	else
		h5_addr <= bl_h_addr + 1;

always @(posedge sclk)
	if (bl_h_addr > h_block_max - 2)
		h6_addr <= h_block_max;
	else
		h6_addr <= bl_h_addr + 2;

always @(posedge sclk)
	if (bl_h_addr > h_block_max - 3)
		h7_addr <= h_block_max;
	else
		h7_addr <= bl_h_addr + 3;

always @(posedge sclk)
	if (bl_h_addr > h_block_max - 4)
		h8_addr <= h_block_max;
	else
		h8_addr <= bl_h_addr + 4;

always @(posedge sclk)
	bl_data <= {h8_rdata[7:0], h7_rdata[7:0], h6_rdata[7:0], h5_rdata[7:0], h4_rdata[7:0], h3_rdata[7:0], h2_rdata[7:0], h1_rdata[7:0], h0_rdata[7:0]};
		
//***************************************************
//				调试信号
//***************************************************
assign	tout = 0;

endmodule       
